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Hynix launches 321-layer NAND (www.electronicsweekly.com)
23 points by WaitWaitWha 2 hours ago | hide | past | web | 13 comments | favorite





Cookie permission dialog is the worst I have encountered in months

Thank god for ublock origin filters, i have all the optional filter lists, I never see those things. EVER.

I just want smaller SPI flash for embedded :( it's been over 10 years since there's been improvement in that space

WLCSP-8 is pretty damn small already, at ~1.5mm square. Hard to get much smaller.

> triple level cell-based 4D memory

What does 4D memory mean?


It’s marketing speak. 3D flash (stacked chips) with the control circuits stacked underneath instead of to the side. So it’s one louder.

https://www.tomshardware.com/news/sk_hynix-debuts-4d_nand,37...


Bigger number = more betterer

Nothing - just marketing. It's their 2nd gen Periphery Under Cell (PUC) device.

Where’s the point where you figure out how to stack chiplets perpendicular to a backplane instead of doing lithography 300 times on the same chip?

That's kind of what we're doing already, although the stacking is parallel, not perpendicular. A lot of the innovation is in how the dies are tied together, cf. https://www.anandtech.com/show/9520/toshiba-brings-throughsi...

When I was in school studying NAND devices (2004-2010) we were quite apprehensive at the long term quantum stability of 4-layer devices.

This (the past 20 years of improvement) is an incredible feat of engineering.


This is 321 physical layers of silicon in an IC, not 321 charge levels.

QLC flash - with 16 charge levels, for four bits per cell - is pretty common nowadays, but that's as far as it goes so far. And stability is indeed a concern; modern flash devices rely heavily on error correction.


Wow. What's the yield like? Are some bits bad and bypassed during testing?

> Are some bits bad and bypassed during testing?

Always. All digital storage media depends on error correcting codes and sector-remapping these days.




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